The present invention relates in general to integrated circuits and in particular to a method and apparatus for testing of integrated circuits.
Integrated circuits are important building blocks of almost all of today's electronic devices. Technology continues to evolve and integrated circuits continue to provide improved functionality. As integrated circuits improve, so do the electronics systems that are built using integrated circuits. There are many types of integrated circuits such as memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic. Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including both combinational and sequential logic. Such logic may include logic gates, products terms, look-up tables, or registers to name just a few. Programmable logic integrated circuits also include embedded user-programmable memory.
Generally, there is a continuing desire to provide both greater functionality and greater performance in programmable logic, as well as in other types of integrated circuits. However, increased levels of integration also result in an integrated circuit's increased susceptibility to defects. Accordingly, improved techniques for testing integrated circuits have been an area of continuously increasing interest. For example, FIG. 1 shows an integrated circuit 100 illustrating a known technique for testing combinational and sequential logic. Integrated circuit 100 includes a combinational and sequential logic block 101 and a built-in self test unit 102. Built-in self test unit 102 is designed to generate test vectors as inputs to logic 101. Logic 101 generates responses to the test vectors that are transmitted back to built-in self test unit 102 for analysis. Based on the responses received from logic 101, built-in self test unit can identify the existence of logic errors that may be caused by defects in the integrated circuit. Individual integrated circuits may then be tested during manufacturing, and devices containing defects can be separated from non-defective devices so that defective products are not sold to customers.
FIG. 2 shows one known circuit for implementing a built-in self testing technique. Built-in self test circuit 200 includes a test pattern generator 201 (“TPG”), logic and register chains 202, and a multiple input signature register 203 (“MISR”). Test vectors are then generated by TPG 201 and applied to the logic to produce output patterns. These output patterns are then received by the MISR 203 and encoded to generate a digital code sometimes referred to as a “signature.” The signature is compared to a “golden signature,” which is developed in advance, and corresponds to a signature that should be generated by the logic when there are no defects. The signature produced by the logic during test is compared to the “golden signature” to determine whether or not the logic under test contains defects. The problem with the use of “golden signatures,” however, is that the output responses become so highly encoded that it becomes almost impossible to extract information about the cause of the error. In particular, it is impossible to determine either the particular logic elements that contain the fault or the test vector that generated the fault.
Therefore, there is a need for an improved method and apparatus for testing of integrated circuits.